1. Field of the Invention:
The invention relates to a method for filling depressions in a surface of a semiconductor structure, and to a semiconductor structure filled in this way.
Semiconductor structures, when utilized as integrated circuits, are produced from patterned layers arranged positionally precisely one above the other. Since the structures in these layers have a thickness in the range from 0.1 xcexcm to 1 xcexcm it is necessary to planarize the surface before a new structure is formed, in order to avoid steep steps for layer application. Such steep steps are disadvantageous particularly when the intention is to deposit a metal layer for interconnecting the circuit elements in the semiconductor structure. On a stepped surface, the thickness of the metallization layer at steep edges is often very small on account of the limited conformity of the sputtering coating used for applying the metal. As a result, the interconnect cross-sections become significantly smaller than on a planar surface. The current intensity then greatly increases in such narrowed interconnect regions, which can lead to rapid ageing of the interconnects. Furthermore, there is also the risk of edge tearing occurring when the interconnect runs over a step, on account of incomplete coverage of the step.
The reflow technique of doped silicate glasses is generally used for the planarization of the semiconductor structures before the implementation of the first metallization plane. In this case, the silicate glasses are principally doped with phosphorus (PSG) or with boron and phosphorus (BPSG). These glasses begin to flow at high temperatures, as a result of which even narrow depressions in the semiconductor surface can be filled. A method of this type is described e.g. in U.S. Pat. No. 5,858,848.
The doped silicate glass layers are generally fabricated by vapor phase deposition, so-called CVD deposition, on the surface. CVD deposition involves thermal decomposition of chemical compounds which, in toto, contain all of the components of the doped silicate glass layer to be produced. Depending on the supply of pressure and energy, the CVD methods are classified into atmospheric, low-pressure and plasma CVD deposition. After the application of the doped silicate glass layer, the latter is then subjected to a high-temperature step, in which the required temperature essentially depends on the phosphorus content. In the case of a temperature treatment of BPSG with a boron and phosphorus content of respectively approximately 4% at 800 to 850xc2x0 C. for 20 to 30 min, depressions having a width of up to 0.15 xcexcm and a depth/width ratio of 5:1 can be filled in a manner free from cavities.
In order to prevent the doping atoms from diffusing from the silicate glass, in particular during the high-temperature step, into the underlying semiconductor layer, a diffusion barrier layer is produced on the surface of the semiconductor structure prior to the deposition of the doped silicate glass layer. Because of its outstanding barrier effect, silicon nitride is generally used as an intermediate layer. In this case, the silicon nitride is deposited in a similar manner to the doped silicate glass in CVD reactors. In this case, the LPCVD method (xe2x80x9clow pressurexe2x80x9d CVD method) and the plasma-enhanced CVD method (PECVD) are preferably used as CVD process for producing silicon nitride. In the LPCVD method, the silicon nitride deposition is effected with SiH2Cl2 as a silicon source, in which a process temperature of 700xc2x0 C. to 800xc2x0 C. is on the semiconductor surface and a pressure of 20 to 40 Pa is in the reactor. In contrast to the LPCVD method, the PECVD nitride deposition utilizes SiH4 as a silicon source, in which the process temperature is approximately 300xc2x0 C. In order to be able to decompose the source gas in the PECVD method, the gas is additionally excited with the aid of a high-frequency gas discharge. The PECVD process and the LPCVD process produce a silicon nitride layer with high conformity, with the result that a layer having essentially the same thickness is produced on the entire semiconductor surface.
However, the silicon nitride layer increases the depth/width ratio of the depressions on the semiconductor surface, which are intended to be filled with the doped silicate glass in a manner free from cavities. The result of this is that in the event of further miniaturization of the semiconductor structures with widths of less than 0.15 xcexcm, the depth/width ratio will be far in excess of the limit value of 5:1 at which the depressions of the semiconductor structures can be filled in a manner free from cavities using the known reflow technique of doped silicate glasses. Although it is possible to achieve improved flowing of the doped silicate glass layer by using temperatures of above 800xc2x0 C. during the heating step, at such temperatures there is a risk that the electrical parameters of the components in the semiconductor structure will be greatly changed or that the latter will be destroyed.
It is accordingly an object of the invention to provide a semiconductor structure and a method for filling depressions in the surface of the semiconductor structure which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type. In particular, it is an object of the invention to enable improved filling of depressions in the surface of a semiconductor structure, in particular below the first metal plane, which makes it possible for the depressions to be filled in a manner free from cavities even with structure widths of less than 0.15 xcexcm and large depth/width ratios.
With the foregoing and other objects in view there is provided, in accordance with the invention a method of filling depressions on the surface of a semiconductor structure, in particular below the first metal plane. A diffusion barrier layer is produced on the semiconductor surface, preferably with the aid of plasma-enhanced vapor phase deposition, during which the ions contained in the plasma are accelerated perpendicularly toward the surface in order to build up the diffusion barrier layer. The effect thereby achieved is that the diffusion barrier layer grows primarily on the areas which run parallel to the surface, and to a lesser extent on vertical structure areas. By virtue of the invention""s non-conformal deposition of the diffusion barrier layer on the semiconductor surface, the depth/width ratio is reduced for the planarization layer that is subsequently to be applied, with the result that depressions can be reliably filled even in the case of semiconductor structures having a width of less than 0.15 xcexcm.
In accordance with an added mode of the invention, it is also possible, in particular, to utilize conventionally used silicon nitride as a diffusion barrier and to use BPSG as a planarization layer. Furthermore, oxynitride may also be used as a diffusion barrier. This means that the filling technique according to the invention can easily be integrated into the various known fabrication methods for semiconductor circuits.
In accordance with an another mode of the invention, during the vapor phase deposition for producing the diffusion barrier layer, the plasma contains at least 1*1010 ions/cm3. This high plasma density makes it possible to achieve particularly high non-conformity of the deposition of the diffusion barrier layer in the depressions.
With the foregoing and other objects in view there is also provided, in accordance with the invention a semiconductor structure that includes: a substrate having a structure plane with depressions formed therein defining vertical surfaces and horizontal surfaces; a diffusion barrier layer; and a planarization layer filing the depressions. The planarization layer is disposed on the diffusion layer. The diffusion barrier layer has a layer thickness on the horizontal surfaces and a layer thickness on the vertical surfaces that is smaller than the layer thickness on the horizontal surfaces.
In accordance with an added feature of the invention, a first metallization plane is disposed above the structure plane.
In accordance with an additional feature of the invention, the diffusion barrier layer is made from silicon nitride and the planarization layer is made from doped silicate glass.
In accordance with a concomitant feature of the invention, the doped silicate glass is BPSG.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for filling depressions in a surface of a semiconductor structure, and a semiconductor structure filled in this way, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.